![]() ![]() Glesner, HADES-High Level Architecture Development and Exploration System First Great Lake Symposium on VLSI, Kalamazoo, Michigan, pp. ![]() Walters, Computer Aided Prototyping for ASIC-based Systems, IEEE Design and Test of Computers, June 1991 This process is experimental and the keywords may be updated as the learning algorithm improves. These keywords were added by machine and not by the authors. In this paper emphasis is put on high level synthesis aspects for the ASIP emulation part of the whole system. The spectrum of realizations ranges from single task software implementations on a single standard processor to application specific integrated processors in a heterogeneous multi-processor environment. User guided and automated synthesis tools generate a fully functional prototype that can be connected to the mechanical subsystem to estimate system performance. ![]() System partitioning into a set of software and hardware modules is done at system description level. This paper presents a design methodology to support the design of embedded information processing units in mechatronic systems during early design phases. ![]()
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